1. Field of the Invention
The present invention relates to programmable logic circuits, and in particular, relates to the configuration of input/output resources in a programmable logic circuit.
2. Discussion of the Related Art
Two examples of high density programmable logic arrays are the programmable Large Scale Integration (pLSI) devices and the in-system programmable Large Scale Integration (ispLSI) devices from Lattice Semiconductor Corporation, Hillsboro, Oreg. An ispLSI device is reprogrammable in its application without being removed from the circuit board. In-system programming techniques are discussed in U.S. Pat. No. 4,855,954 (entitled "In-system Programmable Logic Device with Four Dedicated Terminals" to Turner et al, issued Aug. 8, 1989), U.S. Pat. No. 4,761,768 (entitled "Programmable Logic Device" to Turner et al, issued Aug. 2, 1988), and U.S. Pat. No. 4,896,296 (entitled "Programmable Logic Device Configurable I/O Cell", to Turner et al, issued Jan. 23, 1990). The in-system programming techniques discussed in these U.S. Patents are hereby incorporated by reference. Programmable logic devices can also be implemented in both volatile and nonvolatile memory technologies (e.g. electrical eraseable programmable read-only memory or E.sup.2 PROM).
FIG. 1a shows a block diagram of a prior art device 100, which can be implemented as either a pLSI device or an ispLSI device. As shown in FIG. 1a, device 100 comprises 32 generic logic blocks (GLBs) A0-A7, B0-B7, C0-C7 and D0-D7. Each GLB includes a number of input terminals, a logic array for implementing logic functions and a number of output terminals. The signals at the GLB's input terminals originate either from the routing pool 101, or directly from input/output (I/O) pins, which are shown in FIG. 1 around the periphery of the device, e.g. I/O pin 102a. The signals of the output terminals of a GLB can be routed to both output routing pool 103 and routing pool 101. Output routing pool 103 routes signals between a group of GLBs and a group of I/O pins. Each I/O pin of pLSI device 100 is associated with an input/output cell ("I/O cell"), which is programmable to define whether the I/O pin is an input pin, an output pin or a bidirectional pin.
Routing pool 101 is an interconnection resource for interconnection among the GLBs. Routing pool 101 receives input signals from both the I/O pins and the output terminals of the GLBs and provides the signals received to the input terminals of the GLBs. Routing pool 101 provides connectivity between any pair of GLBs in pLSI device 100.
In FIG. 1a, four groups of GLBs A0-A7, B0-B7, C0-C7 and D0-D7 are shown. Each group of GLBs, together with its output routing pool, the associated I/O cells, and the associated I/O pins, form a structure called a "macroblock". In the prior art, the signal received at each I/O cell is routed to one input terminal of routing pool 101. In addition, two additional input pins are provided per megablock to receive two additional signals into global routing pool.